path: root/ppu.c

static uint8_t memory_read_dma(struct nes_state *state, uint32_t offset);


static void ppu_sprite_shift(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;

	if(!(ppu->reg_mask & 0x10)) {
		return;
	}

	for(uint32_t i = 0; i < ppu->sprite_count; i++) {
		if(ppu->sprite_positions[i] > 0) {
			ppu->sprite_positions[i]--;
		} else {
			ppu->sprite_shift_lo[i] <<= 1;
			ppu->sprite_shift_hi[i] <<= 1;
		}
	}
}


static void ppu_reset(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	memset(ppu, 0, sizeof(struct ppu_state));

}

static uint32_t ppu_resolve_ciram(struct nes_state *state, uint32_t addr) {
	// Apply mirroring logic to address in $2000–$2FFF range
	addr &= 0x0fff;

	switch(state->ines.mirroring) {
		case MIRROR_VERTICAL:
			return (addr & 0x0800) | (addr & 0x03ff); // $2000/$2800 → $0000, $2400/$2C00 → $0400
		case MIRROR_HORIZONTAL:
			return ((addr & 0x0400) >> 1) | (addr & 0x03ff); // $2000/$2400 → $0000, $2800/$2C00 → $0400
		default:
			return addr & 0x07ff; // For now, 4-screen = direct
	}
}

static uint8_t ppu_ciram_read(struct nes_state *state, uint32_t addr) {
	return state->ppu.ciram[ppu_resolve_ciram(state, addr)];
}

static void ppu_ciram_write(struct nes_state *state, uint32_t addr, uint8_t value) {
	state->ppu.ciram[ppu_resolve_ciram(state, addr)] = value;
}


static void ppu_write_2000(struct nes_state *state, uint8_t value) {
	struct ppu_state *ppu = &state->ppu;
	ppu->reg_ctrl = value;
	ppu->temp_addr = (ppu->temp_addr & 0xf3ff) | ((value & 0x03) << 10);
}

static void ppu_write_2001(struct nes_state *state, uint8_t value) {
	state->ppu.reg_mask = value;
}

static void ppu_write_2003(struct nes_state *state, uint8_t value) {
	state->ppu.oam_addr = value;
}

static void ppu_write_2004(struct nes_state *state, uint8_t value) {
	state->ppu.oam[state->ppu.oam_addr] = value;
	state->ppu.oam_addr++;
}

static void ppu_write_2005(struct nes_state *state, uint8_t value) {
	struct ppu_state *ppu = &state->ppu;

	if(ppu->write_latch == 0) {
		ppu->fine_x = value & 0x07;
		ppu->temp_addr = (ppu->temp_addr & ~0x001f) | (value >> 3);
		ppu->write_latch = 1;
	} else {
		ppu->temp_addr = (ppu->temp_addr & ~0x73e0) | ((value & 0x07) << 12) | ((value & 0xf8) << 2);
		ppu->write_latch = 0;
	}
}

static void ppu_write_2006(struct nes_state *state, uint8_t value) {
	struct ppu_state *ppu = &state->ppu;

	if(ppu->write_latch == 0) {
		ppu->temp_addr = (ppu->temp_addr & 0x00ff) | ((value & 0x3f) << 8);
		ppu->write_latch = 1;
	} else {
		ppu->temp_addr = (ppu->temp_addr & 0xff00) | value;
		ppu->vram_addr = ppu->temp_addr;
		ppu->write_latch = 0;
	}
}

static void ppu_write_2007(struct nes_state *state, uint8_t value) {
	struct ppu_state *ppu = &state->ppu;
	uint32_t addr = ppu->vram_addr & 0x3fff;

	if(addr < 0x2000) {
		// CHR-RAM, skip
	} else if(addr < 0x3f00) {
		uint32_t mirrored_addr = addr & 0x0fff;
		ppu->ciram[mirrored_addr & 0x7ff] = value;
	} else if(addr < 0x4000) {
		uint32_t pal_addr = addr & 0x1f;
		if((pal_addr & 0x13) == 0x10) {
			pal_addr &= ~0x10;
		}
		ppu->palette[pal_addr] = value;
	}

	ppu->vram_addr += (ppu->reg_ctrl & 0x04) ? 32 : 1;
}

static uint8_t ppu_read_2002(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	uint8_t result = ppu->reg_status;

	ppu->reg_status &= ~0x80;
	ppu->write_latch = 0;

	return result;
}

static uint8_t ppu_read_2004(struct nes_state *state) {
	return state->ppu.oam[state->ppu.oam_addr];
}

static uint8_t ppu_read_2007(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	uint32_t addr = ppu->vram_addr & 0x3fff;
	uint8_t result = 0;

	// Read from CHR-RAM (CHR-ROM in PPU)
	if(addr < 0x2000) {
		result = ppu->vram_read_buffer;
		ppu->vram_read_buffer = state->chrrom[addr];
	} else if(addr < 0x3f00) {
		// Read from CIRAM (internal VRAM)
		uint32_t mirrored_addr = addr & 0x0fff;
		if(state->ines.mirroring == 2) {
			mirrored_addr |= (addr & 0x0800) ? 0x400 : 0x000; // Handle 4-screen mirroring
		}
		result = ppu->ciram[mirrored_addr & 0x7ff];
	} else if(addr < 0x4000) {
		// Read from palette
		uint32_t pal_addr = addr & 0x1f;
		if((pal_addr & 0x13) == 0x10) {
			pal_addr &= ~0x10; // Skip over the unused area of the palette
		}
		result = ppu->palette[pal_addr];
	}

	// Update VRAM address based on control register
	ppu->vram_addr += (ppu->reg_ctrl & 0x04) ? 32 : 1;
	return result;
}

static void ppu_evaluate_sprites(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	uint8_t sprite_height = (ppu->reg_ctrl & 0x20) ? 16 : 8;
	uint8_t n = 0;

	for(uint8_t i = 0; i < 64; i++) {
		uint8_t y = ppu->oam[i * 4 + 0];
		int row = (int)ppu->scanline - y;

		if(row >= 0 && row < sprite_height) {
			if(n < 8) {
				uint8_t *src = ppu->oam + i * 4;
				uint8_t *dst = ppu->secondary_oam + n * 4;
				dst[0] = src[0];
				dst[1] = src[1];
				dst[2] = src[2];
				dst[3] = src[3];
				ppu->sprite_indexes[n] = i;
				if(i == 0) {
					ppu->sprite_zero_hit_possible = 1;
				}
				n++;
			} else {
				ppu->reg_status |= 0x20;
				break;
			}
		}
	}

	ppu->sprite_count = n;
}

static void ppu_fetch_sprite_patterns(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	for(uint8_t i = 0; i < ppu->sprite_count; i++) {
		uint8_t *s = ppu->secondary_oam + i * 4;
		uint8_t y = s[0], tile = s[1], attr = s[2], x = s[3];
		uint8_t row = ppu->scanline - y;
		uint8_t height = (ppu->reg_ctrl & 0x20) ? 16 : 8;

		if(attr & 0x80) {
			row = height - 1 - row;
		}

		uint32_t addr;
		if(height == 16) {
			uint32_t bank = (tile & 1) ? 0x1000 : 0x0000;
			tile &= 0xfe;
			if(row >= 8) {
				tile++;
				row -= 8;
			}
			addr = bank + tile * 16 + row;
		} else {
			uint32_t bank = (ppu->reg_ctrl & 0x08) ? 0x1000 : 0x0000;
			addr = bank + tile * 16 + row;
		}

		uint8_t lsb = state->chrrom[addr];
		uint8_t msb = state->chrrom[addr + 8];

		if(attr & 0x40) {
			lsb = ((lsb * 0x0202020202ULL & 0x010884422010ULL) % 1023) & 0xff;
			msb = ((msb * 0x0202020202ULL & 0x010884422010ULL) % 1023) & 0xff;
		}

		ppu->sprite_shift_lo[i] = lsb;
		ppu->sprite_shift_hi[i] = msb;
		ppu->sprite_positions[i] = x;
		ppu->sprite_priorities[i] = (attr >> 5) & 1;
	}
}

static void ppu_render_pixel(struct nes_state *state) {
	uint8_t bg_pixel = 0;
	uint8_t bg_palette = 0;
	uint8_t sp_pixel = 0;
	uint8_t sp_palette = 0;
	uint8_t sp_prio = 0;
	uint8_t sp_zero = 0;
	uint8_t final_color = 0;

	struct ppu_state *ppu = &state->ppu;

	uint32_t x = ppu->dot - 1;
	uint32_t y = ppu->scanline;

	if(x >= 256 || y >= 240) {
		return;
	}

	uint32_t bit = 0x8000 >> ppu->fine_x;

	if(ppu->reg_mask & 0x08) {
		uint8_t p0 = (ppu->bg_shift_pattern_low & bit) ? 1 : 0;
		uint8_t p1 = (ppu->bg_shift_pattern_high & bit) ? 1 : 0;
		bg_pixel = (p1 << 1) | p0;

		uint8_t a0 = (ppu->bg_shift_attrib_low & bit) ? 1 : 0;
		uint8_t a1 = (ppu->bg_shift_attrib_high & bit) ? 1 : 0;
		bg_palette = (a1 << 1) | a0;
	}

	if(ppu->reg_mask & 0x10) {
		for(uint8_t i = 0; i < ppu->sprite_count; i++) {
			if(ppu->sprite_positions[i] == 0) {
				uint8_t p0 = (ppu->sprite_shift_lo[i] & 0x80) ? 1 : 0;
				uint8_t p1 = (ppu->sprite_shift_hi[i] & 0x80) ? 1 : 0;
				sp_pixel = (p1 << 1) | p0;

				if(sp_pixel) {
					sp_palette = ppu->secondary_oam[i * 4 + 2] & 3;
					sp_prio = ppu->sprite_priorities[i];
					sp_zero = (ppu->sprite_indexes[i] == 0);
					break;
				}
			}
		}
	}

	if(bg_pixel == 0 && sp_pixel == 0) {
		final_color = ppu->palette[0];
	} else if(bg_pixel == 0 && sp_pixel != 0) {
		final_color = ppu->palette[0x10 | (sp_palette << 2) | sp_pixel];
	} else if(bg_pixel != 0 && sp_pixel == 0) {
		final_color = ppu->palette[(bg_palette << 2) | bg_pixel];
	} else {
		if(sp_zero && ppu->sprite_zero_hit_possible && x < 255) {
			ppu->reg_status |= 0x40;
		}
		if(sp_prio == 0) {
			final_color = ppu->palette[0x10 | (sp_palette << 2) | sp_pixel];
		} else {
			final_color = ppu->palette[(bg_palette << 2) | bg_pixel];
		}
	}
	assert(y*256+x <= 256*240);
	ppu->pixels[y * 256 + x] = final_color;
}

static void ppu_tick(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;

	uint32_t dot = ppu->dot;
	uint32_t scanline = ppu->scanline;

	uint8_t rendering = (ppu->reg_mask & 0x18) != 0;

	if(rendering && scanline < 240 && dot >= 1 && dot <= 256) {
		ppu_render_pixel(state);
	}

	if(rendering && ((dot >= 2 && dot <= 257) || (dot >= 322 && dot <= 337))) {
		ppu_sprite_shift(state);
		ppu->bg_shift_pattern_low <<= 1;
		ppu->bg_shift_pattern_high <<= 1;
		ppu->bg_shift_attrib_low <<= 1;
		ppu->bg_shift_attrib_high <<= 1;
	}

	if(scanline < 240 || scanline == 261) {
		if(rendering && ((dot >= 1 && dot <= 256) || (dot >= 321 && dot <= 336))) {
			switch(dot % 8) {
				case 1: {
					uint32_t nt_addr = 0x2000 | (ppu->vram_addr & 0x0fff);
					ppu->bg_next_tile_id = ppu->ciram[nt_addr & 0x07ff];
					break;
				}
				case 3: {
					uint32_t attr_addr = 0x23c0 | (ppu->vram_addr & 0x0c00) | ((ppu->vram_addr >> 4) & 0x38) | ((ppu->vram_addr >> 2) & 0x07);
					uint8_t attr = ppu->ciram[attr_addr & 0x07ff];
					uint8_t shift = ((ppu->vram_addr >> 4) & 4) | (ppu->vram_addr & 2);
					ppu->bg_next_tile_attrib = (attr >> shift) & 3;
					break;
				}
				case 5: {
					uint32_t base = (ppu->reg_ctrl & 0x10) ? 0x1000 : 0x0000;
					uint32_t tile = ppu->bg_next_tile_id;
					uint32_t fine_y = (ppu->vram_addr >> 12) & 7;
					uint32_t addr_lsb = (base + tile * 16 + fine_y) & 0x1fff;
					ppu->bg_next_tile_lsb = state->chrrom[addr_lsb];
					break;
				}
				case 7: {
					uint32_t base = (ppu->reg_ctrl & 0x10) ? 0x1000 : 0x0000;
					uint32_t tile = ppu->bg_next_tile_id;
					uint32_t fine_y = (ppu->vram_addr >> 12) & 7;
					uint32_t addr_msb = (base + tile * 16 + fine_y + 8) & 0x1fff;
					ppu->bg_next_tile_msb = state->chrrom[addr_msb];
					break;
				}
				case 0: {
					ppu->bg_shift_pattern_low = (ppu->bg_shift_pattern_low & 0xff00) | ppu->bg_next_tile_lsb;
					ppu->bg_shift_pattern_high = (ppu->bg_shift_pattern_high & 0xff00) | ppu->bg_next_tile_msb;

					uint8_t a = ppu->bg_next_tile_attrib;
					ppu->bg_shift_attrib_low = (ppu->bg_shift_attrib_low & 0xff00) | ((a & 1) ? 0xff : 0x00);
					ppu->bg_shift_attrib_high = (ppu->bg_shift_attrib_high & 0xff00) | ((a & 2) ? 0xff : 0x00);

								if((ppu->vram_addr & 0x001f) == 31) {
				ppu->vram_addr &= ~0x001f;
				ppu->vram_addr ^= 0x0400;
			} else {
				ppu->vram_addr++;
			}

					break;
				}
			}
		}

		if(rendering) {
			if(dot == 256) {
				if((ppu->vram_addr & 0x7000) != 0x7000) {
					ppu->vram_addr += 0x1000;
				} else {
					ppu->vram_addr &= ~0x7000;
					uint32_t y = (ppu->vram_addr & 0x03e0) >> 5;
					if(y == 29) {
						y = 0;
						ppu->vram_addr ^= 0x0800;
					} else if(y == 31) {
						y = 0;
					} else {
						y++;
					}
					ppu->vram_addr = (ppu->vram_addr & ~0x03e0) | (y << 5);
				}
			}

			if(dot == 257) {
				ppu->vram_addr = (ppu->vram_addr & ~0x041f) | (ppu->temp_addr & 0x041f);
			}

			if(scanline == 261 && dot >= 280 && dot <= 304) {
				ppu->vram_addr = (ppu->vram_addr & ~0x7be0) | (ppu->temp_addr & 0x7be0);
			}

			if(dot == 257 && scanline < 240) {
				ppu_evaluate_sprites(state);
			}

			if(dot == 340 && scanline < 240) {
				ppu_fetch_sprite_patterns(state);
			}
		}
	}

	if(scanline == 241 && dot == 1) {
		ppu->reg_status |= 0x80;
		if(ppu->reg_ctrl & 0x80) {
			state->nmi_pending = 1;
		}
	}

	if(scanline == 261 && dot == 1) {
		ppu->reg_status &= ~0x80;
		ppu->reg_status &= ~0x40;
		ppu->sprite_zero_hit_possible = 0;
	}

	dot++;
	if(dot > 340) {
		dot = 0;
		scanline++;
		if(scanline > 261) {
			scanline = 0;
			ppu->frame_ready = 1;
		}
	}

	ppu->dot = dot;
	ppu->scanline = scanline;
}

static void ppu_dma_4014(struct nes_state *state, uint8_t page) {
	uint32_t base = page << 8;

	// Add 1 or 2 idle cycles depending on current CPU cycle
	uint8_t idle_cycles = (state->cycle & 1) ? 1 : 2;
	for(uint8_t i = 0; i < idle_cycles; i++) {
		state->cycle++;
		ppu_tick(state); ppu_tick(state); ppu_tick(state);
	}

	for(uint32_t i = 0; i < 256; i++) {
		uint32_t addr = base + i;

		// First CPU cycle (read, ticks only)
		state->cycle++;
		ppu_tick(state); ppu_tick(state); ppu_tick(state);

		// Perform read
		uint8_t value = memory_read_dma(state, addr);

		// Second CPU cycle (write)
		ppu_write_2004(state, value);

		state->cycle++;
		ppu_tick(state); ppu_tick(state); ppu_tick(state);
	}
}