static uint8_t __attribute__((aligned(64))) ppu_bitreverse_lut[256] = {
#   define R2(n)     n,     n + 2*64,     n + 1*64,     n + 3*64
#   define R4(n) R2(n), R2(n + 2*16), R2(n + 1*16), R2(n + 3*16)
#   define R6(n) R4(n), R4(n + 2*4 ), R4(n + 1*4 ), R4(n + 3*4 )
    R6(0), R6(2), R6(1), R6(3)
};
#undef R2
#undef R4
#undef R6

static uint8_t memory_read_dma(struct nes_state *state, uint32_t offset);

static void ppu_reset(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	memset(ppu, 0, sizeof(struct ppu_state));
}

__attribute__((always_inline, hot))
static inline void ppu_write(struct nes_state *state, uint32_t offset, uint8_t value) {
	struct ppu_state *ppu = &state->ppu;

	switch(offset & 7) {
		case 0: {		// 2000
			ppu->reg_ctrl = value;
			ppu->temp_addr = (ppu->temp_addr & 0xf3ff) | ((value & 0x03) << 10);
			ppu->open_bus = value;
		} break;

		case 1: {		// 2001
			ppu->reg_mask = value;
			ppu->open_bus = value;
		} break;

		case 3: {		// 2003
			ppu->oam_addr = value;
		} break;

		case 4: {		// 2004
			ppu->oam[ppu->oam_addr] = value;
			ppu->oam_addr++;
		} break;

		case 5: {		// 2005
			if(ppu->write_latch == 0) {
				ppu->fine_x = value & 0x07;
				ppu->temp_addr = (ppu->temp_addr & ~0x001f) | (value >> 3);
				ppu->write_latch = 1;
			} else {
				ppu->temp_addr = (ppu->temp_addr & ~0x73e0) | ((value & 0x07) << 12) | ((value & 0xf8) << 2);
				ppu->write_latch = 0;
			}
			ppu->open_bus = value;
		} break;

		case 6: {		// 2006
			if(ppu->write_latch == 0) {
				ppu->temp_addr = (ppu->temp_addr & 0x00ff) | ((value & 0x3f) << 8);
				ppu->write_latch = 1;
			} else {
				ppu->temp_addr = (ppu->temp_addr & 0xff00) | value;
				ppu->vram_addr = ppu->temp_addr;
				ppu->write_latch = 0;
			}
			ppu->open_bus = value;
		} break;

		case 7: {		// 2007
			uint32_t addr = ppu->vram_addr & 0x3fff;
			if(addr < 0x2000) {
				// CHR-RAM, skip
			} else if(addr < 0x3f00) {
				state->mapper.ciram_write(state, addr, value);
			} else if(addr < 0x4000) {
				uint32_t pal_addr = addr & 0x1f;
				if((pal_addr & 3) == 0) {
					pal_addr &= ~0x10;
				}
				ppu->palette[pal_addr] = value;
			}
			ppu->vram_addr += (ppu->reg_ctrl & 0x04) ? 32 : 1;
		} break;
	}
}

__attribute__((always_inline, hot))
static inline uint8_t ppu_read(struct nes_state *state, uint32_t offset) {
	struct ppu_state *ppu = &state->ppu;
	uint8_t result = ppu->open_bus;

	switch(offset & 7) {
		case 2: {		// 2002
			result = ppu->reg_status;
			ppu->reg_status &= ~0x80;
			ppu->write_latch = 0;
		} break;

		case 4: {		// 2004
			result = ppu->oam[ppu->oam_addr];
		} break;

		case 7: {		// 2007
			uint32_t addr = ppu->vram_addr & 0x3fff;
			result = 0;

			if(addr < 0x2000) {
				result = ppu->vram_read_buffer;
				ppu->vram_read_buffer =  state->mapper.chr_read(state, addr);
			} else if(addr < 0x3f00) {
				result = state->mapper.ciram_read(state, addr);
			} else if(addr < 0x4000) {
				uint32_t pal_addr = addr & 0x1f;
				if((pal_addr & 0x13) == 0x10) {
					pal_addr &= ~0x10;
				}
				result = ppu->palette[pal_addr];
			}

			ppu->vram_addr += (ppu->reg_ctrl & 0x04) ? 32 : 1;
		} break;
	}
	ppu->open_bus = result;
	return result;
}

__attribute__((hot))
static void ppu_evaluate_sprites(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	uint8_t sprite_height = (ppu->reg_ctrl & 0x20) ? 16 : 8;
	uint8_t n = 0;

	uint8_t *src = ppu->oam;
	uint8_t *dst = ppu->secondary_oam;
	for(uint8_t i = 0; i < 64; i++) {
		uint8_t y = src[0];
		int32_t row = (int32_t)ppu->scanline - y;

		if(row >= 0 && row < sprite_height) {
			if(n < 8) {
				dst[0] = src[0];
				dst[1] = src[1];
				dst[2] = src[2];
				dst[3] = src[3];
				ppu->sprite_indexes[n] = i;
				ppu->sprite_zero_hit_possible |= (i == 0);

				dst += 4;
				n++;
			} else {
				ppu->reg_status |= 0x20;
				break;
			}
		}
		src += 4;
	}

	ppu->sprite_count = n;
}

__attribute__((hot))
static void ppu_fetch_sprite_patterns(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;
	uint32_t addr;
	uint32_t bank;

	uint8_t *s = ppu->secondary_oam;
	uint8_t height = (ppu->reg_ctrl & 0x20) ? 16 : 8;

	for(uint8_t i = 0; i < ppu->sprite_count; i++) {
		uint8_t y = s[0], tile = s[1], attr = s[2], x = s[3];
		uint8_t row = ppu->scanline - y;

		row = (attr & 0x80) ? height - 1 - row : row;

		if(height == 16) {
			bank = (tile & 1) << 12;
			tile &= 0xfe;
			if(row >= 8) {
				tile++;
				row -= 8;
			}
		} else {
			bank = (ppu->reg_ctrl & 0x08) << 9;
		}
		addr = bank + tile * 16 + row;

		uint8_t lsb = state->mapper.chr_read(state, addr);
		uint8_t msb = state->mapper.chr_read(state, addr + 8);

		if(attr & 0x40) {
			lsb = ppu_bitreverse_lut[lsb];
			msb = ppu_bitreverse_lut[msb];
		}

		ppu->sprite_shift_lo[i] = lsb;
		ppu->sprite_shift_hi[i] = msb;
		ppu->sprite_positions[i] = x;
		ppu->sprite_priorities[i] = attr & 0x20;
		s += 4;
	}
}

__attribute__((hot))
static void ppu_render_pixel(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;

	uint32_t x = ppu->dot - 1;
	uint32_t y = ppu->scanline;

	// Fine X shift mask
	// static const uint16_t fine_shift[8] = { 0x8000, 0x4000, 0x2000, 0x1000, 0x0800, 0x0400, 0x0200, 0x0100 };
	uint16_t bit = 0x8000 >> ppu->fine_x;//fine_shift[ppu->fine_x];

	uint8_t bg_pixel = 0;
	uint8_t bg_palette = 0;
	uint8_t sp_pixel = 0;
	uint8_t sp_palette = 0;
	uint8_t sp_prio = 0;
	uint8_t sp_zero = 0;

#if 1		// TODO(peter): Decide what I prefer, masking away unlikely path, or LIKELY hint to the compiler
	uint8_t bg_mask = (ppu->reg_mask & 0x08) ? 0xff : 0x00;
	uint8_t sp_mask = (ppu->reg_mask & 0x10) ? 0xff : 0x00;

	// Background
	uint8_t p0 = !!(ppu->bg_shift_pattern_low & bit);
	uint8_t p1 = !!(ppu->bg_shift_pattern_high & bit);
	uint8_t a0 = !!(ppu->bg_shift_attrib_low & bit);
	uint8_t a1 = !!(ppu->bg_shift_attrib_high & bit);

	bg_pixel   = ((p1 << 1) | p0) & bg_mask;
	bg_palette = ((a1 << 1) | a0) & bg_mask;

	// Sprite
	for(uint8_t i = 0; i < ppu->sprite_count; i++) {
		if(ppu->sprite_positions[i]) continue;

		uint8_t lo = ppu->sprite_shift_lo[i];
		uint8_t hi = ppu->sprite_shift_hi[i];
		sp_pixel = (((hi & 0x80) >> 6) | ((lo & 0x80) >> 7)) & sp_mask;

		if(!sp_pixel) continue;

		sp_palette = ppu->secondary_oam[i * 4 + 2] & 3;
		sp_prio    = ppu->sprite_priorities[i];
		sp_zero    = (ppu->sprite_indexes[i] == 0);
		break;
	}
#else
	// Background fetch
	if(LIKELY(ppu->reg_mask & 0x08)) {
		uint8_t p0 = !!(ppu->bg_shift_pattern_low & bit);
		uint8_t p1 = !!(ppu->bg_shift_pattern_high & bit);
		bg_pixel = (p1 << 1) | p0;

		uint8_t a0 = !!(ppu->bg_shift_attrib_low & bit);
		uint8_t a1 = !!(ppu->bg_shift_attrib_high & bit);
		bg_palette = (a1 << 1) | a0;
	}

	// Sprite fetch
	if(LIKELY(ppu->reg_mask & 0x10)) {
		for(uint8_t i = 0; i < ppu->sprite_count; i++) {
			if(ppu->sprite_positions[i]) continue;

			uint8_t lo = ppu->sprite_shift_lo[i];
			uint8_t hi = ppu->sprite_shift_hi[i];
			sp_pixel = ((hi & 0x80) >> 6) | ((lo & 0x80) >> 7);

			if(!sp_pixel) continue;

			sp_palette = ppu->secondary_oam[i * 4 + 2] & 3;
			sp_prio    = ppu->sprite_priorities[i];
			sp_zero    = (ppu->sprite_indexes[i] == 0);
			break;
		}
	}
#endif
	// Final pixel composition
	uint8_t palette_index = 0;
	uint8_t bg_index = (bg_palette << 2) + bg_pixel;
	uint8_t sp_index = (sp_palette << 2) + sp_pixel;
	uint8_t selector = (bg_pixel ? 2 : 0) | (sp_pixel ? 1 : 0);

	switch(selector) {
		case 0: { palette_index = 0;						} break;
		case 1: { palette_index = 0x10 | sp_index;	} break;
		case 2: { palette_index = bg_index;				} break;
		case 3: {
			if(sp_zero && ppu->sprite_zero_hit_possible && x < 255) {
				ppu->reg_status |= 0x40;
			}
			palette_index = (sp_prio) ? bg_index : 0x10 | sp_index;
		} break;
	}

	state->pixels[y * 256 + x] = ppu->palette[palette_index];		// NOTE(peter): Add color_emphasis bits (expand palette to 8x).
}

__attribute__((hot, flatten))
static void ppu_tick(struct nes_state *state) {
	struct ppu_state *ppu = &state->ppu;

	uint32_t dot = ppu->dot;
	uint32_t scanline = ppu->scanline;
	uint8_t rendering = (ppu->reg_mask & 0x18);

	for(uint32_t ppu_loops = 0; ppu_loops < 3; ++ppu_loops) {

		if(LIKELY(rendering)) {

			if(ppu->even_frame && dot == 0) {
				// call mapper_tick here.
				ppu->dot++;
			}

			if(scanline < 240 && dot >= 1 && dot <= 256) {
				ppu_render_pixel(state);
			}

			if(scanline < 240 || scanline == 261) {
				if((dot >= 1 && dot <= 256) || (dot >= 321 && dot <= 336)) {

					if(ppu->reg_mask & 0x10) {
						for(uint32_t i = 0; i < ppu->sprite_count; i++) {
							if(ppu->sprite_positions[i] > 0) {
								ppu->sprite_positions[i]--;
							} else {
								ppu->sprite_shift_lo[i] <<= 1;
								ppu->sprite_shift_hi[i] <<= 1;
							}
						}
					}

					ppu->bg_shift_pattern_low <<= 1;
					ppu->bg_shift_pattern_high <<= 1;
					ppu->bg_shift_attrib_low <<= 1;
					ppu->bg_shift_attrib_high <<= 1;

					switch(dot % 8) {
						case 1: {
							uint32_t nt_addr = 0x2000 | (ppu->vram_addr & 0x0fff);
							ppu->bg_next_tile_id = state->mapper.ciram_read(state, nt_addr);
							break;
						}
						case 3: {
							uint32_t attr_addr = 0x23c0 | (ppu->vram_addr & 0x0c00) | ((ppu->vram_addr >> 4) & 0x38) | ((ppu->vram_addr >> 2) & 0x07);
							uint8_t attr = state->mapper.ciram_read(state, attr_addr & 0x0fff);
							uint8_t shift = ((ppu->vram_addr >> 4) & 4) | (ppu->vram_addr & 2);
							ppu->bg_next_tile_attrib = (attr >> shift) & 3;
							break;
						}
						case 5: {
							uint32_t base = (ppu->reg_ctrl & 0x10) ? 0x1000 : 0x0000;
							uint32_t tile = ppu->bg_next_tile_id;
							uint32_t fine_y = (ppu->vram_addr >> 12) & 7;
							uint32_t addr_lsb = (base + tile * 16 + fine_y) & 0x1fff;
							ppu->bg_next_tile_lsb = state->mapper.chr_read(state, addr_lsb);
							break;
						}
						case 7: {
							uint32_t base = (ppu->reg_ctrl & 0x10) ? 0x1000 : 0x0000;
							uint32_t tile = ppu->bg_next_tile_id;
							uint32_t fine_y = (ppu->vram_addr >> 12) & 7;
							uint32_t addr_msb = (base + tile * 16 + fine_y + 8) & 0x1fff;
							ppu->bg_next_tile_msb =  state->mapper.chr_read(state, addr_msb);
							break;
						}
						case 0: {
							ppu->bg_shift_pattern_low = (ppu->bg_shift_pattern_low & 0xff00) | ppu->bg_next_tile_lsb;
							ppu->bg_shift_pattern_high = (ppu->bg_shift_pattern_high & 0xff00) | ppu->bg_next_tile_msb;

							uint8_t a = ppu->bg_next_tile_attrib;
							ppu->bg_shift_attrib_low = (ppu->bg_shift_attrib_low & 0xff00) | ((a & 1) ? 0xff : 0x00);
							ppu->bg_shift_attrib_high = (ppu->bg_shift_attrib_high & 0xff00) | ((a & 2) ? 0xff : 0x00);

							if((ppu->vram_addr & 0x001f) == 31) {
								ppu->vram_addr &= ~0x001f;
								ppu->vram_addr ^= 0x0400;
							} else {
								ppu->vram_addr++;
							}

							break;
						}
					}
				}

				if(dot == 256) {
					if((ppu->vram_addr & 0x7000) != 0x7000) {
						ppu->vram_addr += 0x1000;
					} else {
						ppu->vram_addr &= ~0x7000;
						uint32_t y = (ppu->vram_addr & 0x03e0) >> 5;
						if(y == 29) {
							y = 0;
							ppu->vram_addr ^= 0x0800;
						} else if(y == 31) {
							y = 0;
						} else {
							y++;
						}
						ppu->vram_addr = (ppu->vram_addr & ~0x03e0) | (y << 5);
					}
				}

				if(dot == 257) {
					ppu->vram_addr = (ppu->vram_addr & ~0x041f) | (ppu->temp_addr & 0x041f);
				}

				if(UNLIKELY(scanline == 261) && dot >= 280 && dot <= 304) {
					ppu->vram_addr = (ppu->vram_addr & ~0x7be0) | (ppu->temp_addr & 0x7be0);
				}

				if(dot == 257 && LIKELY(scanline < 240)) {
					ppu_evaluate_sprites(state);
				}

				if(dot == 340 && (LIKELY(scanline < 240) || UNLIKELY(scanline == 261))) {
					ppu_fetch_sprite_patterns(state);
				}
			}
		}

		if(UNLIKELY(scanline == 241) && dot == 1) {
			ppu->reg_status |= 0x80;
			if(ppu->reg_ctrl & 0x80) {
				state->nmi_pending = 1;
			}
		}

		if(UNLIKELY(scanline == 261) && dot == 1) {
			ppu->reg_status &= ~0x80;
			ppu->reg_status &= ~0x40;
			ppu->sprite_zero_hit_possible = 0;
		}

		dot++;
		if(dot > 340) {
			dot = 0;
			scanline++;
			if(scanline > 261) {
				scanline = 0;
				ppu->frame_ready = 1;
				ppu->even_frame = !ppu->even_frame;
			}
		}

		ppu->dot = dot;
		ppu->scanline = scanline;
	}
}

__attribute__((always_inline, hot))
static inline void ppu_dma_4014(struct nes_state *state, uint8_t page) {
	uint32_t base = page << 8;

	// Add 1 or 2 idle cycles depending on current CPU cycle
	uint8_t idle_cycles = (state->cycles & 1) ? 1 : 2;
	for(uint8_t i = 0; i < idle_cycles; i++) {
		state->cycles++;
		ppu_tick(state);
	}

	for(uint32_t i = 0; i < 256; i++) {
		uint32_t addr = base + i;

		state->cycles++;
		ppu_tick(state);
		uint8_t value = memory_read_dma(state, addr);

		state->cycles++;
		ppu_tick(state);
		// ppu_write_2004(state, value);
		ppu_write(state, 4, value);
	}
}